Smart write algorithm to enhance performances and reliability of a RRAM macro
Résumé
This paper presents a comprehensive assessment of the impact of various design assist techniques on the inherent performance and reliability of native RRAM on silicon. The collaborative optimization of design and technology plays a crucial role in replacing conventional flash memory as the leading solution. We showcase that employing read-before-write, current-limitation, and write-termination techniques result in reductions of power consumption during programming operations by 47%, 56%, and 13% respectively. Through their combination with write verification and error correction code mechanisms, these enhancements collectively achieve 87% reduction in energy consumption and a notable 55% decrease in access time. These advancements are made possible by the introduction of a novel smart write algorithm (SWA). Leveraging a representative 128kb RRAM macro implemented in 130nm CMOS technology, this study significantly contributes to the feasible integration of RRAM for embedded applications. Experimental assessments on silicon validate the increased reliability, with a demonstrated 28.1µA read margin after undergoing 1 million cycles without encountering any read errors, maintaining a Bit Error Rate (BER) below 10-7.
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